design_check_schematic_pcb_parity

SERVERAltium-MCP-Suite SOURCEM-R-Abedini/Altium-MCP-Suite

Low RISK CLASS

Category Read

Parameters 00 required

Recommended Allowedsee the rule below

Registry record Grade F, identity unverified Pull the record →

This record as markdown: /tools/altium-mcp-suite/design-check-schematic-pcb-parity.md

WHAT IT DOES

What design_check_schematic_pcb_parity does on Altium-MCP-Suite

AI agents call design_check_schematic_pcb_parity to retrieve information from Altium-MCP-Suite without modifying anything. It is typically the context-gathering step in research, monitoring, and reporting workflows, before the agent takes action elsewhere.

RISK

Why design_check_schematic_pcb_parity is rated Low

Even though design_check_schematic_pcb_parity only reads data, uncontrolled read access leaks sensitive information and racks up API costs: an agent caught in a retry loop can make thousands of calls a minute without anyone noticing.

Attacks that exploit this kind of access

RECOMMENDED RULE

The rule that runs design_check_schematic_pcb_parity safely

PolicyLayer is an MCP gateway: it sits between your AI agents and Altium-MCP-Suite, and checks every tool call against a rule you set before the call runs. Nothing changes on the server itself. For design_check_schematic_pcb_parity, this is the rule to start with:

design_check_schematic_pcb_parity Allowed

design_check_schematic_pcb_parity is read-only, so it stays allowed. Everything else on the server is denied unless you say otherwise.

View as policy code

policy.json

{
  "version": "1",
  "default": "deny",
  "tools": {
    "design_check_schematic_pcb_parity": {}
  }
}

ALLOW ONLY THIS TOOL → Instant setup, no code required.

The button opens the PolicyLayer dashboard: create your workspace, connect Altium-MCP-Suite, apply this rule, and every design_check_schematic_pcb_parity call is checked against it from then on.

FAQ

Questions about design_check_schematic_pcb_parity

What does the design_check_schematic_pcb_parity tool do? +

Compare schematic snapshot with {components:[pcb_get_component_pads results],complete:true}. Waivers require component,pin,code,reason and expected net (default empty). Shared-pin net mismatches cannot be waived. Incomplete input cannot pass. It is categorised as a Read tool in the Altium-MCP-Suite MCP Server, which means it retrieves data without modifying state.

How do I enforce a policy on design_check_schematic_pcb_parity? +

Register the Altium-MCP-Suite MCP server in PolicyLayer and add a rule for design_check_schematic_pcb_parity: allow, deny, rate-limit, or require approval. Point your MCP client at the PolicyLayer proxy URL and the rule is enforced on every call, before it reaches Altium-MCP-Suite. Nothing to install.

What risk level is design_check_schematic_pcb_parity? +

design_check_schematic_pcb_parity is a Read tool with low risk. Read-only tools are generally safe to allow by default.

Can I rate-limit design_check_schematic_pcb_parity? +

Yes. Add a rate_limit block to the design_check_schematic_pcb_parity rule in your PolicyLayer policy. For example, setting max: 10 and window: 60 limits the tool to 10 calls per minute. Rate limits are tracked per agent session and reset automatically.

How do I block design_check_schematic_pcb_parity completely? +

Set action: deny in the PolicyLayer policy for design_check_schematic_pcb_parity. The AI agent will receive a policy violation error and cannot call the tool. You can also include a reason field to explain why the tool is blocked.

What MCP server provides design_check_schematic_pcb_parity? +

design_check_schematic_pcb_parity is provided by the Altium-MCP-Suite MCP server (M-R-Abedini/Altium-MCP-Suite). PolicyLayer sits as a proxy in front of this server to enforce policies before tool calls reach the server.

KEEP EXPLORING

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